1. Field of the Invention
The invention relates to the field of data communications and, more particularly, to recognizing a synchronization word or flag during data transfers over a very noisy communications channel.
2. Description of Related Art
With the advent of high speed modem technology, such as employed in the V.34 modem design, modems now have the capability of adaptively selecting from a set of data transmission rates from 2400 to 33600 bits/second. This allows the modems to operate over a wide variety of communications channels, ranging from almost noise-free to very-noisy. However, before the high speed data rate can be established, the modems are typically required to exchange critical modem capability information using a robust low speed protocol. Examples of the use of such low speed protocols are the use of the 300 bits/second V.21 modem during V.8 bis handshaking, the use of 600 bits/second differential phase shift keying (DPSK) during Phase-2/V.34, and the use of low speed quadrature amplitude modulation (QAM) during Phase -4/V.34, to name a few.
For the transmission of the capabilities information, a V.34 modem typically transmits one or more frames of bit-error protected data. For example, The INFOO, INFO1C, and INFO1A sequences used during Phase-2/V.34 consist of "Fill Bits", a "Frame-sync" byte, several information bits, and finally, the cylic-redundancy-check (CRC) word. The receiving modem is required to synchronize it's receiver on the frame-sync byte and then ensure that the trailing capabilities data passes the CRC check. This may require the receiver to compensate for channel distortions and then establish bit timing so that the data can be correctly sampled. The general procedures for the transmission and detection of such a frame of CRC protected data is well known to those skilled in the pertinent art.
Consider the example of implementation of the 600 bits/second DPSK receiver structure used in phase-2 of the V.34 modem. One may approach this bit decoding problem by employing a correlation demodulator followed by a bit sampler. This type of a DPSK detection receiver is well known in the pertinent art. In this approach, the time required for the convergence of the bit sampler may be of the order of several bits, especially under very noisy conditions. Under the condition that the establishment of the bit sampling timing cannot be achieved, the received bits may be in error, requiring one or more retransmissions of the transmitted data frames. This causes undesirable delays in the modem startup sequence.
The problem of establishing the correct sample timing may be alleviated under certain conditions by buffering up the sample data until satisfactory convergence of the timing tracker has been achieved, then correctly sampling the buffered data to produce the correct transmitted frame. However, this may lead to increased buffering resources requirements and/or peaky processor loading, which may be undesirable from a systems standpoint.